| Manufacturer | INTEL Super Computers |
| Identification,ID | Touchstone Delta |
| Date of first manufacture | 1990 |
| Number produced | one |
| Estimated price or cost | - |
| location in museum | - |
Contents of this page:
| Intel Touchstone Delta |
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Massively Parallel with Intel's 32-bit 80860 RISC chip, performing at 60 MFLOPS peak
MIMD hypercube.
MIMD is for Multiple Instruction Multiple Data
from http://netlib2.cs.utk.edu/utk/papers/sign/node8.html
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from http://nhse.npac.syr.edu/hpccsurvey/orgs/intel/intel.html#Touchstone-Delta
Touchstone Delta Overview of Platform: The Touchstone Delta System It should be noted that this is a research prototype for the Paragon system and is not intended for commercial production. Architecture: Distributed Memory MIMD hypercube. Node: Intel's 32-bit 80860 RISC chip, performing at 60 MFLOPS peak, with 8--16 Mbytes of memory. Features include pipelining and instruction caching but these make it difficult to approach peak performance. Topology: A mesh with wormhole routing. Operating System: MACH, Express and CrOS III are available. Communication Paradigms: Extensions for explicit message passing are available. Languages: C and Fortran. Programming Environment: Tools are available for debugging, code parallelizing and profiling. Performance: Peak performance is 32 GFLOPS for the maximum configuration of 484 nodes. Delta has achieved the highest LINPACK rating ever, with 13.9 GFLOPS, and until recently held the record for the SLALOM benchmark, with 5750 patches.
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Historical Notes
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This Specimen
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from http://208.201.97.5/pubs/fcw/1998/0525/fcw-mktdelta-5-25-1998.html
from http://208.201.97.5/pubs/fcw/1998/0525/fcw-mktdelta-5-25-1998.html
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Updated May 29, 2001